Freescale Semiconductor /MK70F12 /DDR /CR03

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CR03

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LATLIN0LATGATE0WRLAT0TCCD

Description

DDR Control Register 3

Fields

LATLIN

Latency Linear

2 (0010): 1 cycle

3 (0011): 1.5 cycles

15 (1111): 7.5 cycles

LATGATE

Latency Gate

WRLAT

Write Latency

TCCD

Time CAS-to-CAS Delay

Links

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